Thursday, September 30, 2010

Atmel AVR instruction set

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Arithmetic operations work on registers R0-R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
AVR instruction set
Arithmetic Bit & Others Transfer Jump Branch Call
ADD Rd, Rr
ADC Rd, Rr
ADIW Rd+1:Rd, K6

SUB Rd, Rr

SUBI Rd, K8
SBC Rd, Rr
SBCI Rd, K8
SBIW Rd+1:Rd, K6

INC Rd

DEC Rd

AND Rd, Rr

ANDI Rd, K8
OR Rd, Rr
ORI Rd, K8
EOR Rd, Rr

COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rd, K8
SWAP Rd

LSR Rd

ROR Rd
ASR Rd

MUL Rd, Rr
MULS Rd, Rr
MULSU Rd, Rr
FMUL Rd, Rr
FMULS Rd, Rr
FMULSU Rd, Rr


BSET s
BCLR s
SBI A, b
CBI A, b
BST Rd, b
BLD Rd, b

NOP

BREAK
SLEEP
WDR
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr

IN Rd, A

OUT A, Rr

PUSH Rr

POP Rr

LDI Rd, K8

LDS Rd, K16

LD Rd, X

LD Rd, -X
LD Rd, X+

LDD Rd, Y+K6

LD Rd, -Y
LD Rd, Y+

LDD Rd, Z+K6

LD Rd, -Z
LD Rd, Z+

STS K16, Rr


ST X, Rr

ST -X, Rr
ST X+, Rr

STD Y+K6, Rr

ST -Y, Rr
ST Y+, Rr

STD Z+K6, Rr

ST -Z, Rr
ST Z+, Rr

LPM

LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+

SPM

RJMP K12
IJMP
EIJMP
JMP K22
CPSE Rd, Rr

SBRC Rr, b

SBRS Rr, b

SBIC A, b

SBIS A, b

BRBC s, K7

BRBS s, K7
RCALL K12
ICALL
EICALL
CALL K22

RET

RETI


[edit] Instruction set inheritance

Not all instructions are implemented in all AVR controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
Family Members Arithmetic Branches Transfers Bit-Wise
Minimal Core AT90S1200
ATtiny10
ATtiny11
ATtiny12
ATtiny15
ATtiny28
ADD
ADC
SUB
SUBI
SBC
SBCI
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
RJMP
RCALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
LD
ST
MOV
LDI
IN
OUT
LPM
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
Classic Core up to 8K Program Space AT90S2313
AT90S2323
ATtiny22
AT90S2333
AT90S2343
AT90S4414
AT90S4433
AT90S4434
AT90S8515
AT90C8534
AT90S8535
ATtiny26
ATmega8515
new instructions:
ADIW
SBIW
new instructions:
IJMP
ICALL
new instructions:
LD (now 9 modes)
LDD
LDS
ST (9 modes)
STD
STS
PUSH
POP
(nothing new)
Classic Core with up to 128K ATmega103
ATmega603
AT43USB320
AT76C711
(nothing new) new instructions:
JMP
CALL
new instructions:
ELPM
(nothing new)
Enhanced Core with up to 8K ATmega8
ATmega83
ATmega85
new instructions:
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
(nothing new) new instructions:
MOVW
LPM (3 modes)
SPM
(nothing new)
Enhanced Core with up to 128K ATmega16
ATmega161
ATmega163
ATmega32
ATmega323
ATmega64
ATmega128
AT43USB355
AT94 (FPSLIC)

AT90CAN series
AT90PWM series
ATmega48
ATmega88

ATmega168
ATmega162
ATtiny13
ATtiny25
ATtiny45
ATtiny85
ATtiny2313
ATmega164
ATmega324
ATmega328
ATmega644
ATmega165
ATmega169
ATmega325
ATmega3250
ATmega645
ATmega6450
ATmega406
(nothing new) (nothing new) (nothing new) new instructions:
BREAK
Enhanced Core with up to 4M ATmega640
ATmega1280
ATmega1281
ATmega2560
ATmega2561
(nothing new) new instructions:
EIJMP
EICALL
(nothing new) (nothing new)
XMEGA core ATxmega series new instructions:
DES
(nothing new) (nothing new) (nothing new)

[edit] See also

[edit] External links

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