Friday, October 1, 2010

TI MSP430


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TI MSP430
Designer Texas Instruments
Bits 16-bit
Type Memory-Memory
Registers
16, R0 - Program Counter, R1 - Stack Pointer, R2 - Status Register, R2/R3 - Constant Generator
Photo of two experimenter boards for the MSP430 chipset by Texas Instruments. On the left the larger chip version, on the right a small version in USB format.
The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, and specifically, low power consumption[1] embedded applications. The architecture dates from the 1990s and is reminiscent of the DEC PDP-11.The MSP430 is particularly well suited for metering, wireless radio frequency engineering (RF), or battery-powered applications.

Contents

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 Applications

The MSP430 is a popular choice among hardware designers for low powered embedded devices. The electric current drawn in idle mode can be less than 1 microamp. The top CPU speed is 25 MHz. It can be throttled back for lower power consumption. The MSP430 also utilizes six different Low-Power Modes, which can disable unneeded clocks and CPU. This allows the MSP430 to sleep, while its peripherals continue to work without the need for an energy hungry processor. Additionally, the MSP430 is capable of wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption. Note that MHz is not equivalent to Million instructions per second (MIPS), and different architectures can obtain different MIPS rates at lower CPU clock frequencies, which can result in lower dynamic power consumption for an equivalent amount of digital processing.
The device comes in a variety of configurations featuring the usual peripherals: internal oscillator, timer including PWM, watchdog, USART, SPI, I2C, 10/12/14/16-bit ADCs, and brownout reset circuitry. Some less usual peripheral options include comparators (that can be used with the timers to do simple ADC), on-chip op-amps for signal conditioning, 12-bit DAC, LCD driver, hardware multiplier, USB, and DMA for ADC results. Apart from some older EPROM (PMS430E3xx) and high volume mask ROM (MSP430Cxxx) versions, all of the devices are in-system programmable via JTAG or a built in bootstrap loader (BSL) using RS-232.
There are, however, limitations that prevent it from being used in more complex embedded systems. The MSP430 does not have an external memory bus, so is limited to on-chip memory (up to 256 KB Flash memory and 16 KB RAM) which might be too small for applications that require large buffers or data tables. Also, although it has a very capable DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe[2].

 MSP430 generations

MSP430 Nomenclature
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There are five general generations of MSP430 processors. In order of development, they were the '3xx generation, the '1xx generation, the '4xx generation, the '2xx generation, and the '5xx generation. The digit after the generation identifies the model (generally higher model numbers are larger and more capable), the third digit identifies the amount of memory on board, and the fourth, if present, identifies a minor model variant. The most common variation is a different on-chip analog-to-digital converter.
The 3xx and 1xx generations were limited to a 16 bit address space. In the later generations this was expanded to include '430X' instructions that allow a 20 bit address space. As happened with the PDP-11, and as one might expect, extending the addressing range beyond the 16 bit word size introduced some peculiarities and inefficiencies for programs larger than 64 kBytes.
In the following list, it helps to think of the typical 200 mA·Hr capacity of a CR2032 lithium coin cell as 200,000 μA·Hr, or 22.8 μA·year. Thus, considering only the CPU draw, such a battery could supply a 0.7 μA current draw for 32 years. (In reality, battery self-discharge would reduce this number.)
The significance of the 'RAM retention' vs the 'real-time clock mode' is that in real time clock mode the CPU can go to sleep with a clock running which will wake it up at a specific future time. In RAM retention mode, some external signal is required to wake it, e.g. I/O pin signal or SPI slave receive interrupt.

 MSP430x1xx Series

The MSP430x1xx Series is the basic generation without an embedded LCD controller. They are generally smaller than the '3xx generation. These Flash or ROM based Ultra-Low Power MCUs offer 8 MIPS, 1.8–3.6 V operation, up to 60 KB Flash, and a wide range of high-performance analog and intelligent digital peripherals.
  • Power specs - As low as
    • 0.1 μA RAM retention
    • 0.7 μA real-time clock mode
    • 200 μA / MIPS active
    • Feature Fast Wake-Up From Standby Mode in <6 μs
  • Device Parameters
    • Flash Options: 1–60 KiB
    • ROM Options: 1–16 KiB
    • RAM Options: 512 B–10 KiB
    • GPIO Options: 14, 22, 48 pins
    • ADC Options: Slope, 10 & 12-bit SAR
    • Other Integrated peripherals: Analog Comparator, DMA, Hardware Multiplier, SVS, 12-bit DAC

 MSP430F2xx Series

The MSP430F2xx Series are similar to the '1xx generation, but operate at even lower power, support up to 16 MHz operation, and have a more accurate (±2%) on-chip clock that makes it easier to operate without an external crystal. These Flash-based Ultra-Low Power offer 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-up/pull-down resistors, and low-pin count options.
  • Power Specs Overview, as low as:
    • 0.1 μA RAM retention
    • 0.3 μA Standby mode (VLO)
    • 0.7 μA real-time clock mode
    • 220 μA / MIPS active
    • Feature Ultra-Fast Wake-Up From Standby Mode in <1 μs
  • Device Parameters
    • Flash Options: 1–120 KiB
    • RAM Options: 128 B–8 KiB
    • GPIO Options: 10, 16, 24, 32, 48, 64 pins
    • ADC Options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta
    • Other Integrated peripherals: Analog Comparator, Hardware Multiplier, DMA, SVS, 12-bit DAC, Op Amps

 MSP430G2xx Series

The MSP430G2xx Value Series features flash-based Ultra-Low Power MCUs up to 16 MIPS with 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-up/pull-down resistors, and low-pin count options, at lower prices than the MSP430F2xx series.
  • Ultra-Low Power, as low as (@2.2V):
    • 0.1 μA RAM retention
    • 0.4 μA Standby mode (VLO)
    • 0.7 μA real-time clock mode
    • 220 μA / MIPS active
    • Ultra-Fast Wake-Up From Standby Mode in <1 μs
  • Device Parameters
    • Flash Options: 0.5–2 KiB
    • RAM Options: 128 B
    • GPIO Options: 10, 16, 24 pins
    • ADC Options: Slope, 10-bit SAR
    • Other Integrated peripherals: Analog Comparator

 MSP430x3xx Series

The MSP430x3xx Series is the oldest generation, designed for portable instrumentation with an embedded LCD controller. This also includes a frequency-locked loop oscillator that can automatically synchronize to a low-speed (32 kHz) crystal. This generation does not support EEPROM memory, only mask ROM and UV-eraseable and one-time programmable EPROM. Later generations provide only flash ROM and mask ROM options. These devices offer 2.5–5.5 V operation, up to 32 KB ROM.
  • Power Specs Overview, as low as:
    • 0.1 μA RAM retention
    • 0.9 μA real-time clock mode
    • 160 μA / MIPS active
    • Feature Fast Wake-Up From Standby Mode in <6 μs
  • Device Parameters
    • ROM Options: 2–32 KB
    • RAM Options: 512 B–1 KiB
    • GPIO Options: 14, 40 pins
    • ADC Options: Slope, 14-bit SAR
    • Other Integrated peripherals: LCD controller, Hardware Multiplier

 MSP430x4xx Series

The MSP430x4xx Series are similar to the '3xx generation, and also include an integrated LCD controller, but are larger and more capable. These Flash or ROM based devices offers 8-16 MIPS at 1.8–3.6 V operation, with FLL, and SVS. Ideal for low power metering and medical applications.
  • Power Specs Overview, as low as:
    • 0.1 μA RAM retention
    • 0.7 μA real-time clock mode
    • 200 μA / MIPS active
    • Feature Fast Wake-Up From Standby Mode in <6 μs
  • Device Parameters
    • Flash/ROM Options: 4 kB – 120 KB
    • RAM Options: 256 B – 8 KB
    • GPIO Options: 14, 32, 48, 56, 68, 72, 80 pins
    • ADC Options: Slope, 10 &12-bit SAR, 16-bit Sigma Delta
    • Other Integrated peripherals: LCD Controller, Analog Comparator, 12-bit DAC, DMA, Hardware Multiplier, Op Amp, USCI Modules

 MSP430x5xx Series

The MSP430x5xx Series are able to run up to 25 MHz, have up to 256 kB flash memory and up to 16 kB RAM. This new Flash-based family features the lowest active power consumption with up to 25 MIPS at 1.8-3.6 V operation (165 uA/MIPS). Includes an innovative Power Management Module for optimal power consumption. Many devices feature integrated USB.
  • Power Specs Overview, as low as:
    • 0.1 μA RAM retention
    • 2.5 μA real-time clock mode
    • 165 μA / MIPS active
    • Feature Fast Wake-Up From Standby Mode in <5 μs
  • Device Parameters:
    • Flash Options: up to 256 KB
    • RAM Options: up to 16 KB
    • ADC Options: 10 & 12-bit SAR
    • Other Integrated peripherals: USB, Analog Comparator, DMA, Hardware Multiplier, RTC, USCI, 12-bit DAC
Note that when the flash size is over 64K words (128 KBytes), instruction addresses can no longer be encoded in just two bytes. This change in pointer size causes some incompatibilities with previous parts.

 MSP430 CPU

The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers.[3] R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R3 always reads as 0 and writes to it are ignored. R4 through R15 are available for general use.
The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
MSP430 instruction set
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction

0 0 0 1 0 0 opcode B/W As register Single-operand arithmetic
0 0 0 1 0 0 0 0 0 B/W As register RRC Rotate right (1 bit) through carry
0 0 0 1 0 0 0 0 1 0 As register SWPB Swap bytes
0 0 0 1 0 0 0 1 0 B/W As register RRA Rotate right (1 bit) arithmetic
0 0 0 1 0 0 0 1 1 0 As register SXT Sign extend byte to word
0 0 0 1 0 0 1 0 0 B/W As register PUSH Push value onto stack
0 0 0 1 0 0 1 0 1 0 As register CALL Subroutine call; push PC and move source to PC
0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 RETI Return from interrupt; pop SR then pop PC

0 0 1 condition 10-bit signed offset Conditional jump; PC = PC + 2×offset
0 0 1 0 0 0 10-bit signed offset JNE/JNZ Jump if not equal/zero
0 0 1 0 0 1 10-bit signed offset JEQ/JZ Jump if equal/zero
0 0 1 0 1 0 10-bit signed offset JNC/JLO Jump if no carry/lower
0 0 1 0 1 1 10-bit signed offset JC/JHS Jump if carry/higher or same
0 0 1 1 0 0 10-bit signed offset JN Jump if negative
0 0 1 1 0 1 10-bit signed offset JGE Jump if greater or equal
0 0 1 1 1 0 10-bit signed offset JL Jump if less
0 0 1 1 1 1 10-bit signed offset JMP Jump (unconditionally)

opcode source Ad B/W As destination Two-operand arithmetic
0 1 0 0 source Ad B/W As destination MOV Move source to destination
0 1 0 1 source Ad B/W As destination ADD Add source to destination
0 1 1 0 source Ad B/W As destination ADDC Add source and carry to destination
0 1 1 1 source Ad B/W As destination SUBC Subtract source from destination (with carry)
1 0 0 0 source Ad B/W As destination SUB Subtract source from destination
1 0 0 1 source Ad B/W As destination CMP Compare (pretend to subtract) source from destination
1 0 1 0 source Ad B/W As destination DADD Decimal add source to destination (with carry)
1 0 1 1 source Ad B/W As destination BIT Test bits of source AND destination
1 1 0 0 source Ad B/W As destination BIC Bit clear (dest &= ~src)
1 1 0 1 source Ad B/W As destination BIS Bit set (logical OR)
1 1 1 0 source Ad B/W As destination XOR Exclusive or source with destination
1 1 1 1 source Ad B/W As destination AND Logical AND source with destination (dest &= src)
Instructions are 16 bits, followed by up to two 16-bit extension words. There are four addressing modes, specified by the 2-bit As field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially.
Indexed addressing modes add a 16-bit extension word to the instruction.
MSP430 addressing modes
As Register Syntax Description
00 n Rn Register direct. The operand is the contents of Rn.
01 n x(Rn) Indexed. The operand is in memory at address Rn+x.
10 n @Rn Register indirect. The operand is in memory at the address held in Rn.
11 n @Rn+ Indirect autoincrement. As above, then the register is incremented by 1 or 2.

Addressing modes using R0 (PC)
01 0 (PC) LABEL Symbolic. x(PC) The operand is in memory at address PC+x.
11 0 (PC) #x Immediate. @PC+ The operand is the next word in the instruction stream.

Addressing modes using R2 (SR) and R3 (CG), special-case decoding
01 2 (SR) &LABEL Absolute. The operand is in memory at address x.
10 2 (SR) #4 Constant. The operand is the constant 4.
11 2 (SR) #8 Constant. The operand is the constant 8.
00 3 (CG) #0 Constant. The operand is the constant 0.
01 3 (CG) #1 Constant. The operand is the constant 1. There is no index word.
10 3 (CG) #2 Constant. The operand is the constant 2.
11 3 (CG) #−1 Constant. The operand is the constant −1.
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC. In the two-operand instructions, there is only one Ad bit to specify the destination addressing mode, so only modes 00 (register direct) and 01 (indexed) are allowed. If both source and destination are indexed, the source extension word comes first.
When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.
The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.

[edit] Pseudo-operations

A number of additional instructions are implemented as alises for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as "MOV @SP+,PC". Emulated instructions are:
MSP430 Emulated instructions
Emulated Actual Description
ADC.x dst ADDC.x #0,dst Add carry to destination
BR dst MOV dst,PC Branch to destination
CLRC BIC #1,SR Clear carry bit
CLRN BIC #4,SR Clear negative bit
CLRZ BIC #2,SR Clear zero bit
DADC.x dst DADD.x #0,dst Decimal add carry to destination
DEC.x dst SUB.x #1,dst Decrement
DECD.x dst SUB.x #2,dst Double decrement
DINT BIC #8,SR Disable interrupts
EINT BIS #8,SR Enable interrupts
INC.x dst ADD.x #1,dst Increment
INCD.x dst ADD.x #2,dst Double increment
INV.x dst XOR.x #−1,dst Invert
NOP MOV #0,R3 No operation
POP dst MOV @SP+,dst Pop from stack
RET MOV @SP+,PC Return from subroutine
RLA.x dst ADD.x dst,dst Rotate left arithmetic (shift left 1 bit)
RLC.x dst ADDC.x dst,dst Rotate left through carry
SBC.x dst SUBC.x #0,dst Subtract borrow (1−carry) from destination
SETC BIS #1,SR Set carry bit
SETN BIS #4,SR Set negative bit
SETZ BIS #2,SR Set zero bit
TST.x dst CMP.x #0,dst Test destination
Note that the immediate constants −1 (0xffff), 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.

[edit] MSP430X 20-bit extension

The basic MSP430 cannot support more memory (ROM + RAM + peripherals) than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions:
  1. A limited number of 20-bit instructions for common operations, and
  2. A general prefix-word mechanism that can extend any instruction to 20 bits.
The extended instructions include some additional capabilities, notably multi-bit shifts and multi-register load/store operations.
20-bit operations use the length suffix ".A" (for address) instead of .B or .W. .W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
MSP430X extended instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Second word Instruction

0 0 0 0 source 0 0 opcode destination
Extended memory-register moves
0 0 0 0 src 0 0 0 0 dst — MOVA @Rsrc,Rdst
0 0 0 0 src 0 0 0 1 dst — MOVA @Rsrc+,Rdst
0 0 0 0 addr[19:16] 0 0 1 0 dst addr[15:0] MOVA &abs20,Rdst
0 0 0 0 src 0 0 1 1 dst x[15:0] MOVA x(Rsrc),Rdst

0 0 0 0 n−1 op. 0 1 0 W/A destination
Bit shifts (1–4 bit positions)
0 0 0 0 n−1 0 0 0 1 0 W/A dst — RRCM.x #n,Rdst (Rotate right through carry.)
0 0 0 0 n−1 0 1 0 1 0 W/A dst — RRAM.x #n,Rdst (Rotate right arithmetic, a.k.a. shift right signed.)
0 0 0 0 n−1 1 0 0 1 0 W/A dst — RLAM.x #n,Rdst (Rotate left arithmetic, a.k.a. shift left.)
0 0 0 0 n−1 1 1 0 1 0 W/A dst — RRUM.x #n,Rdst (Rotate right unsigned, a.k.a. shift right logical.)

0 0 0 0 source 0 1 1 op. destination
Extended register-memory moves
0 0 0 0 src 0 1 1 0 addr[19:16] addr[15:0] MOVA Rsrc,&abs20
0 0 0 0 src 0 1 1 1 dst x[15:0] MOVA Rsrc,x(Rdst)

0 0 0 0 source 1 opcode destination
Extended ALU operations
0 0 0 0 imm[19:16] 1 0 0 0 dst imm[15:0] MOVA #imm20,Rdst
0 0 0 0 imm[19:16] 1 0 0 1 dst imm[15:0] CMPA #imm20,Rdst
0 0 0 0 imm[19:16] 1 0 1 0 dst imm[15:0] ADDA #imm20,Rdst
0 0 0 0 imm[19:16] 1 0 1 1 dst imm[15:0] SUBA #imm20,Rdst
0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst
0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst
0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst
0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst

0 0 0 1 0 0 1 1 op. mode varies
CALLA
0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 — RETI (Same as MSP430)
0 0 0 1 0 0 1 1 0 1 As register
CALLA source
0 0 0 1 0 0 1 1 1 0 0 0 abs[19:16] abs[15:0] CALLA &abs20
0 0 0 1 0 0 1 1 1 0 0 1 x[19:16] x[15:0] CALLA x(PC)
0 0 0 1 0 0 1 1 1 0 1 0 — — (reserved)
0 0 0 1 0 0 1 1 1 0 1 1 imm[19:16] imm[15:0] CALLA #imm20
0 0 0 1 0 0 1 1 1 1 — — (reserved)

0 0 0 1 0 1 dir W/A n−1 register
Push/pop n registers ending with specified
0 0 0 1 0 1 0 W/A n−1 src — PUSHM.x #n,Rsrc  Push Rsrc, R(src−1), ... R(src−n+1)
0 0 0 1 0 1 1 W/A n−1 dst−n+1 — POPM.x #n,Rdst  Pop R(dst−n+1), R(dst−n+2), ... Rdst
All other instructions can have a prefix word added which extends them to 20 bits. The prefix word contains an additional operand size bit, which is combined with the existing B/W bit to specify the operand size. There is one unused size combination; there are indications that this might be used in future for a 32-bit operand size.[4]
The prefix word comes in two formats, and the choice between them depends on the instruction which follows. If the instruction has any non-register operands, then the simple form is used, which provides 2 4-bit fields to extend any offset or immediate constant in the instruction stream.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in (useful for instructions like DADD which always use the carry bit), and a repeat count. A 4-bit field in the extension word encodes either a repeat count (0–15 repetitions in addition to the initial execution), or a register number which contains a 4-bit repeat count.
MSP430X prefix words
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction

0 0 0 1 1 — A/L 0 0 — Extension word
0 0 0 1 1 src[19:16] A/L 0 0 dst[19:16] Memory operand extension
0 0 0 1 1 0 0 ZC 0 A/L 0 0 n−1 Register operand extension (immediate repeat count)
0 0 0 1 1 0 0 ZC 1 A/L 0 0 Rn Register operand extension (register repeat count)

[edit] MSP430 address space

The general layout of the MSP430 address space is:
0x0000–0x0007 
Processor special function registers (interrupt control registers)
0x0008–0x00FF 
8-bit peripherals. These must be accessed using 8-bit loads and stores.
0x0100–0x01FF 
16-bit peripherals. These must be accessed using 16-bit loads and stores.
0x0200–0x09FF 
Up to 2048 bytes of RAM.
0x0C00–0x0FFF 
1024 bytes of bootstrap loader ROM (flash ROM parts only).
0x1000–0x10FF 
256 bytes of data flash ROM (flash ROM parts only).
0x1100–0x38FF 
Extended RAM on models with more than 2048 bytes of RAM. (0x1100–0x18FF is a copy of 0x0200–0x09FF)
0x1100–0xFFFF 
Up to 60 kilobytes of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vectors.
A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes (0x1100–0x18FF) is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.
There is a new extended version of the architecture (called MSP430X) which allows a 20-bit address space. It allows additional program ROM beginning at 0x10000.
The '5xx series has a greatly redesigned address space, with the first 4K devoted to peripherals, and up to 16K of RAM.

[edit] Peripherals

The MSP430 peripherals are generally easy to use, with (mostly) consistent addresses between models, and no write-only registers.

[edit] General-purpose I/O ports 0-10

As is standard on microcontrollers, most pins connect to a more specialized peripheral, but if that peripheral is not needed, the pin may be used for general-purpose I/O. The pins are divided into 8-bit groups called "ports", each of which is controlled by a number of 8-bit registers. In some cases, the ports are arranged in pairs which can be accessed as 16-bit registers.
The MSP430 family defines 11 I/O ports, P0 through P10, although no chip implements more than 10 of them. P0 is only implemented on the '3xx family. P7 through P10 are only implemented on the largest members (and highest pin count versions) of the '4xx and '2xx families. The newest '5xx family has P1 through P11, and the control registers are reassigned to provide more port pairs. Each port is controlled by the following registers. Ports which do not implement particular features (such as interrupt on state change) do not implement the corresponding registers.
PxIN 
Port x input. This is a read-only register, and reflects the current state of the pin.
PxOUT 
Port x output. The values written to this read/write register are driven out the corresponding pins when they are configured to output.
PxDIR 
Port x data direction. Bits written as 1 configure the corresponding pin for output. Bits written as 0 configure the pin for input.
PxSEL 
Port x function select. Bits written as 1 configure the corresponding pin for use by the specialized peripheral. Bits written as 0 configure the pin for general-purpose I/O. Port 0 ('3xx parts only) is not multiplexed with other peripherals and does not have a P0SEL register.
PxREN 
Port x resistor enable ('2xx & '5xx only). Bits set in this register enable weak pull-up or pull-down resistors on the corresponding I/O pins even when they are configured as inputs. The direction of the pull is set by the bit written to the PxOUT register.
PxDS 
Port x drive strength ('5xx only). Bits set in this register enable high-current outputs. This increases output power, but may cause EMI.
Ports 0–2 can produce interrupts when inputs change. Additional registers configure this ability:
PxIES 
Port x interrupt edge select. Selects the edge which will cause the PxIFG bit to be set. When the input bit changes from matching the PxIES state to not matching it (i.e. whenever a bit in PxIES XOR PxIN changes from clear to set), the corresponding PxIFG bit is set.
PxIE 
Port x interrupt enable. When this bit and the corresponding PxIFG bit are both set, an interrupt is generated.
PxIFG 
Port x interrupt flag. Set whenever the corresponding pin makes the state change requested by PxIES. Can be cleared only by software. (Can also be set by software.)
PxIV 
Port x interrupt vector ('5xx only). This 16-bit register is a priority encoder which can be used to handle pin-change interrupts. If n is the lowest-numbered interrupt bit which is pending in PxIFG and enabled in PxIE, this register reads as 2n+2. If there is no such bit, it reads as 0. The scale factor of 2 allows direct use as an offset into a branch table. Reading this register also clears the reported PxIFG flag.
Some pins have special purposes either as inputs or outputs. (For example, timer pins can be configured as capture inputs or PWM outputs.) In this case, the PxDIR bit controls which of the two functions the pin performs when the PxSEL bit is set. If there is only one special function, then PxDIR is generally ignored. The PxIN register is still readable if the PxSEL bit is set, but interrupt generation is disabled. If PxSEL is clear, the special function's input is frozen and disconnected from the external pin. Also, configuring a pin for general-purpose output does not disable interrupt generation.
General-purpose I/O register address map
'1xx–'4xx families

PxIN  PxOUT PxDIR PxSEL PxIES PxIE  PxIFG PxREN
P0 0x10 0x11 0x12
0x13 0x14 0x15
P1 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
P2 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
P3 0x18 0x19 0x1a 0x1b


0x10
P4 0x1c 0x1d 0x1e 0x1f


0x11
P5 0x30 0x31 0x32 0x33


0x12
P6 0x34 0x35 0x36 0x37


0x13
PA P7 0x38 0x3a 0x3c 0x3e


0x14
P8 0x39 0x3b 0x3d 0x3f


0x15
PB P9 0x08 0x0a 0x0c 0x0e


0x16
P10 0x09 0x0b 0x0d 0x0f


0x17
'5xx family

PxIN  PxOUT PxDIR PxREN PxDS  PxSEL PxIV  PxIES PxIE  PxIFG
PA P1 0x200 0x202 0x204 0x206 0x208 0x20A 0x20E 0x218 0x21A 0x21C
P2 0x201 0x203 0x205 0x207 0x209 0x20B 0x21E 0x219 0x21B 0x21D
PB P3 0x220 0x222 0x224 0x226 0x228 0x22A



P4 0x221 0x223 0x225 0x227 0x229 0x22B



PC P5 0x240 0x242 0x244 0x246 0x248 0x24A



P6 0x241 0x243 0x245 0x247 0x249 0x24B



PD P7 0x260 0x262 0x264 0x266 0x268 0x26A



P8 0x261 0x263 0x265 0x267 0x269 0x26B



PE P9 0x280 0x282 0x284 0x286 0x288 0x28A



P10 0x281 0x283 0x285 0x287 0x289 0x28B



P11 0x2A0 0x2A2 0x2A4 0x2A6 0x2A8 0x2AA



PJ 0x320 0x322 0x324 0x326 0x328 4 bits only; shared with JTAG pins.

[edit] Intelligent Peripherals

Analog-to-Digital Converter
The MSP430 line offers two types of Analog-to-Digital Conversion (ADC). 10- and 12-bit Successive Approximation converters, as well as a 16-bit Sigma-Delta converter. Data transfer controllers and a 16 word conversion-and-control buffer allow the MSP430 to convert and store samples without CPU intervention, minimizing power consumption.
Brown Out Reset
The Brown Out Reset circuitry detects low supply voltages and initiates a POR (Power On Reset) signal to reset the device. The MSP430's BOR circuit uses almost no power and is enabled at all times, including in all low power modes.
Comparator A, A+
The MSP430's comparator module provides precision slope Analog-to-Digital Conversions. Monitors external analog signals and provides voltage and resistor value measurement. Capable of selectable power modes.
Digital-to-Analog Converter
The MSP430's Digital-to-Analog Converter module features 8- and 12-bit modes and a programmable settling time for low power optimization. Internal or external reference selection is also possible.
Timers
The MSP 430 has 1 or 2 relatively flexible timers (5xxx series has 3). Each timer has 3 to 7 capture and compare registers that can each be observing the timer count and take a snap shot due to the change in an external signal or cause an external signal to change at a specified timer count. One of the timers can get its clock from an external signal. Timer clocks can not be gated or started and stopped by external signals. The ability to chain timers together to produce complex pulse sequences is limited. Interrupt generation is very flexible.
Direct Memory Access Controller
The MSP430's DMA allows data transfers from one address to another without CPU intervention, across the entire address range. Features up to three independent transfer channels.
Although the MSP430's DMA subsystem is very capable it has several flaws, the most significant of which is the lack of an external transfer strobe. Although a DMA transfer can be triggered externally, there is no external indication of completion of a transfer. Consequently DMA to and from external sources is limited to external trigger per byte transfers, rather than full blocks automatically via DMA. This can lead to significant complexity (as in requiring extensive hand tweaking of code) when implementing processor to processor or processor to USB communications[2]. The reference cited uses an obscure timer mode to generate high speed strobes for DMA transfers. Unfortunately, the timers are not flexible enough to easily make up for the lack of an external DMA transfer strobe.
DMA operations that involve word transfers to byte locations cause truncation to 8 bits rather than conversion to two byte transfers. This makes DMA with A/D or D/A 16 bit values less useful than it could be (although it is possible to DMA these values through port A or B on some versions of the MSP 430 using an externally visible trigger per transfer such as a timer output).
ESP430 (integrated in FE42xx devices)
The ESP430CE module performs metering calculations independent of the CPU. Module has separate SD15, HW multiplier, and embedded processor engine.
LCD/LCD_A/LCD_B
The LCD/LCD_A controller directly drives LCD displays for up to 196 segments. Supports static, 2-mux, 3-mux, and 4-mux LCDs. LCD_A module ihas integrated charge pump for contrast control. LCD_B enables blinking of individual segments with separate blinking memory.
Op Amps
Feature single supply, low current operation with rail-to-rail outputs and programmable settling times. Software selectable configuration options: unity gain mode, comparator mode, inverting PGA, non-inverting PGA, differential and instrumentation amplifier.
Hardware multiplier
Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations. Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch.
The 8 registers used are:
Address Name Function
0x130 MPY Operand1 for unsigned multiply
0x132 MPYS Operand1 for signed multiply
0x134 MAC Operand1 for unsigned multiply-accumulate
0x136 MACS Operand1 for signed multiply-accumulate
0x138 OP2 Second operand for multiply operation
0x13a ResLo Low word of multiply result
0x13c ResHi High word of multiply result
0x13e SumExt Carry out of multiply-accumulate
The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.
If a multiply-accumulate operation is desired, the ResLo and ResHi registers must also be initialized.
Then, each time a write is performed to the OP2 register, a multiply is performed and the result stored or added to the result registers. The SumExt register is a read-only register that contains the carry out of the addition (0 or 1) in case of an unsigned multiply), or the sign extension of the 32-bit sum (0 or -1) in case of a signed multiply. In the case of a signed multiply-accumulate, the SumExt value must be combined with the most significant bit of the prior SumHi contents to determine the true carry out result (-1, 0, or +1).
The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.

[edit] Development tools

Texas Instruments provides various hardware experimenter boards that support large (approximately two centimeters square) and small (approximately one millimeter square) MSP430 chips. TI also provides software development tools, both directly, and in conjunction with partners (see the full list of compilers, assemblers, and IDEs). One such toolchain is the IAR C/C++ compiler and Integrated development environment, or IDE. A Kickstart edition can be downloaded for free from TI or IAR; it is limited to 8 KB of C/C++ code in the compiler and debugger (assembly language programs of any size can be developed and debugged with this free toolchain).
TI also combines a version of its own compiler and tools with its Eclipse-based Code Composer Studio IDE ("CCS"). It sells full-featured versions, and offers a free version for download which has a code size limit of 16 KB. CCS supports in-circuit emulators, and includes a simulator and other tools; it can also work with other processors sold by TI.
The open source community produces a freely available software development toolset (MSPGCC) based on the GNU toolset. There is very early llvm-msp430 project, which may eventually provide better support for MSP430 in LLVM.
Other commercial development tool sets, which include editor, compiler, linker, assembler, debugger and in some cases code wizards, are available. VisSim, a block diagram language for model based development, generates efficient fixed point C-Code directly from the diagram.[5] VisSim generated code for a closed loop ADC+PWM based PID control on the F2013 compiles to less than 1 KB flash and 100 bytes RAM.[6] VisSim has on-chip peripheral blocks for the entire MSP430 family I2C, ADC, SD16, PWM.

[edit] Development platforms

Since the MSP430 is targeted at customers interested in low power solutions to problems, TI has tackled the low-budget problem by offering a very small experimenter board, the eZ430-F2013, on a USB stick. This makes it easy for designers to choose the MSP430 chip for inexpensive development platforms that can be used with a computer. The eZ430-F2013 contains an MSP430F2013 microcontroller on a detachable prototyping board, and accompanying CD with development software. It is helpful for schools, hobbyists and garage inventors. It is also welcomed by engineers in large companies prototyping projects with capital budget problems.
The MSP430F2013 and its siblings are set apart by the fact that it is the only MSP430 part that is available in a dual in-line package (DIP). Other variants in this family are only available in various surface-mount packages. TI has gone to some trouble to support the eZ430 development platform by making the raw chips easily prototypable by hobbyists.
Texas Instruments released the MSP430 Launchpad in July 2010 at the price of $4.30 with free shipping to the United States. The MSP430 Launchpad has an onboard flash emulator, USB, 2 programmable LEDs, and 1 programmable push button.
More information is available at the MSP430 Launchpad wiki.

[edit] Debugging interface

In common with other microcontroller vendors, TI has developed a two-wire debugging interface found on some of their MSP430 parts that can replace the larger JTAG interface. The eZ430 Development Tool contains a full USB-connected Flash Emulation Tool ("FET") for this new two-wire protocol, named "Spy-Bi-Wire" by TI. Spy-Bi-Wire was initially introduced on only the smallest devices in the 'F2xx family with limited number of I/O pins, such as the MSP430F20xx, MSP430F21x2, and MSP430F22x2. The support for Spy-Bi-Wire has been expanded with the introduction of the latest '5xx family, where all devices have support Spy-Bi-Wire interface in addition to JTAG.
The advantage of the Spy-Bi-Wire protocol is that it uses only two communication lines, one of which is the dedicated _RESET line. The JTAG interface on the lower pin count MSP430 parts is multiplexed with general purpose I/O lines. This makes it relatively difficult to debug circuits built around the small, low-I/O-budget chips, since the full 4-pin JTAG hardware will conflict with anything else connected to those I/O lines. This problem is alleviated with the Spy-Bi-Wire-capable chips, which are still compatible with the normal JTAG interface for backwards compatibility with the old development tools.
JTAG debugging and flash programming tools based on OpenOCD and widely used in the ARM community are not available for the MSP430. Programming tools specially designed for the MSP430 are marginally less expensive than JTAG interfaces that use OpenOCD. However, should a project discover midstream that more MIPS, more memory, and more I/O peripherals are needed, those tools will not transfer to a processor from another vendor.

[edit] References

  1. ^ MSP430 will run on grapes - video on YouTube
  2. ^ a b http://www.faculty.uaf.edu/ffdr/pdf/ISAST2009.pdf
  3. ^ "MSP430 Ultra-Low-Power Microcontroller". Texas Instruments. http://www-s.ti.com/sc/techlit/slab034.pdf. Retrieved 2008-07-09. 
  4. ^ The size bit itself is named "A/L", where "L" (long) is used by other processors to indicate 32-bit operands. Also the description of the SXTX instruction (MSP430F5xx Family User's Guide alau208f page 237) describes the effect of the instruction in register bits 20–31.
  5. ^ MSP430 article published in IEEE magazine.
  6. ^ Visual Solutions

[edit] External links

[edit] Community and information sites

[edit] Visual programming C code generators

[edit] Compilers, assemblers and IDEs

[edit] Free Compiler and IDEs

[edit] Most Popular Unrestricted IDEs and Compilers

[edit] Miscellaneous IDEs

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